Site Address
S-178, MIDC, Bhosari
Pune - 411 026.
INDIA
Tel:
+91 20-40767777
Email:
info@evolve-india.com
careers@evolve-india.com
Pune - 411 026.
INDIA
Tel:
+91 20-40767777
Email:
info@evolve-india.com
careers@evolve-india.com
VLSI-Digital Front end Design
System Verilog based Verification Services
ASIC/FPGA/IP Design Services
Evolve can handhold and deploy its services in full RTL to GDSII design path using various software tools of reputed companies such as Synopsys, Magma, Cadence
and mentor Graphics.
The expertises drawn from the industry have a keen sense of adaptation to methodology-based design. Evolve’s senior technical staff have worked with the worlds leading semiconductor design houses both as employees and as design
service professionals and the rich collective experience allows us to offer path to meeting customer objectives in a seamless and non-knee jerk format..
- RTL/ Micro-Architectural definition
- Verilog/VHDL/System Verilog language based coding
- Functional Verification and Test bench development
- Sign-off verification
- FPGA Synthesis and Prototyping
Independent Verification Services
- Regression Testing
- Independent Verification of complete chip
- Independent Verification of blocks
- IP qualification
- Coding Self-checking Test cases
- Development of Custom VIP/Assertion Checkers
- Standalone core or IP verification
- Verification of ASIC/ SoC/ IP
- Developing SystemVerilog based Verification IPs
- Developing SystemVerilog Assertions (SVA)
ASIC/FPGA/IP Design Services
- Architecture to RTL
- FPGA prototyping of SoC/ ASIC Verification
- FPGA-to-ASIC Translation
- FPGA-to-FPGA Translation